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| 21145 phoneline/ethernet lan controller preliminary datasheet product features homepna features n compliant with the home phoneline networking alliance (homepna*) specification effort. n integrates a homepna phy for 1 mb/s ethernet-like home networking on telephone lines. n provides automatic support for dual homepna data transfer rates and dual transmission power levels. n supports autodetection between 10base-t, homepna and mii/sym ports. n generates an interrupt upon homepna phy interrupt. n provides a software interface to the homepna phy internal registers. power management and power saving features n fully compliant with the network device class power management specification , revision 1.0, and the communication device class power management specification , under the onnow architecture for microsofts pc97 design guide , pc 98 hardware design guide, and pc 99 hardware design guide . n supports all wake-up events defined in the network device class power management specification , revision 1.0 and the communication device class power management specification. n fully compliant with the advanced configuration and power interface (acpi) specification , revision 1.0 n fully compliant with the pci bus power management interface specification , revision 1.0. pci and cardbus features n supports pci and cardbus interfaces for network and modem access. n supports cardbus cstschg pin and status changed registers. n supports storage of cardbus card information structure (cis) in the serial rom or the expansion rom. host interface features n includes a powerful onchip direct memory access (dma) with programmable burst size, providing low cpu utilization. n supports interrupt mitigation on transmit and receive. n contains large independent receive and transmit fifos. network side features n supports three network ports: 10base-t (10 mb/s), homepna (1 mb/s), and mii/sym (10/100 mb/s). n supports autodetection between 10base-t, homepna, and mii/sym ports. n supports full-duplex operation on both mii/sym and 10base-t ports. n provides internal and external loopback capability on all network ports. n supports ieee 802.3 and ansi 8802-3 ethernet standards. other features n provides microwire* interface for serial rom (1 k and 4 k eeprom). n incorporates a modem interface that connects to a wide range of modem chipsets available in the marketplace. order number: 278256-001 april 1999 notice: this document contains preliminary information on new products in production. the specifications are subject to change without notice. verify with your local intel sales office that you have the latest datasheet before finalizing a design.
21145 ii preliminary datasheet information in this document is provided in connection with intel products. no license, express or implied, by estoppel or othe rwise, to any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, inte l assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel products including liabil ity or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property righ t. intel products are not intended for use in medical, life saving, or life sustaining applications. intel may make changes to specifications and product descriptions at any time, without notice. the 21145 phoneline/ethernet lan controller may contain design defects or errors known as errata which may cause the product to deviate from published specifications. current characterized errata are available on request. contact your local intel sales office or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are referenced in this document, or other intel literature may be obtaine d by calling 1-800- 548-4725 or by visiting intel's website at http://www.intel.com. copyright ? intel corporation, 1999 *third-party brands and names are the property of their respective owners. preliminary datasheet iii 21145 contents 1.0 introduction................................................................................................................ ......... 1 1.1 manual organization ............................................................................................. 1 1.2 general description............................................................................................... 1 1.3 21145 block diagram ............................................................................................ 2 2.0 pinout and signal descriptions .......................................................................................... 4 2.1 21145 pinout ......................................................................................................... 4 2.2 signal descriptions................................................................................................ 5 2.3 pin tables ...........................................................................................................13 2.4 signal grouping by function ...............................................................................16 3.0 electrical and environmental specifications.....................................................................18 3.1 voltage limit ratings ..........................................................................................18 3.2 temperature limit ratings ..................................................................................18 3.3 oscillator characteristics.....................................................................................18 3.4 power specifications ...........................................................................................19 3.4.1 21145 power specifications ...................................................................19 3.5 pci bus and cardbus electrical parameters ......................................................20 3.5.1 pci and cardbus i/o voltage specifications .........................................20 3.5.2 system bus reset..................................................................................20 3.5.3 pci and cardbus clock specifications ..................................................20 3.5.4 other pci and cardbus signals.............................................................21 3.6 homepna specifications ....................................................................................23 3.6.1 homepna transmit timing parameters (25 c) ...................................23 3.6.2 homepna transmit specifications ........................................................23 3.6.3 homepna receive specifications .........................................................23 3.6.4 homepna receive ac electrical characteristics ..................................24 3.7 twisted-pair dc specifications ...........................................................................24 3.8 serial interface attachment specifications..........................................................25 3.8.1 internal sia mode 10base-t interface timingtransmit ....................25 3.8.2 internal sia mode 10base-t interface timingreceive .....................27 3.8.3 internal sia mode 10base-t interface timingidle link pulse ...........27 3.9 mii interface specifications .................................................................................28 3.10 mii/sym port timing ...........................................................................................29 3.10.1 mii/sym 10/100 mb/s and 10 mb/s timingtransmit...........................29 3.10.2 mii/sym 10/100 mb/s timingreceive ................................................29 3.10.3 sym 10/100 mb/s timingsignal detect ..............................................30 3.10.4 mii 10/100 mb/s timingreceive error ................................................32 3.10.5 mii 10/100 mb/s timingcarrier sense and collision ..........................32 3.11 expansion rom and serial rom port dc specification ....................................33 3.12 expansion rom port timing...............................................................................33 3.12.1 expansion rom read timing................................................................33 3.12.2 expansion rom write timing ................................................................34 3.13 serial rom timing characteristics .....................................................................35 3.14 external register timing .....................................................................................36 3.15 modem electrical parameters .............................................................................37 21145 iv preliminary datasheet 3.16 write access to modem chipset ......................................................................... 37 3.16.1 read access to modem chipset ............................................................ 37 4.0 mechanical specifications................................................................................................ 39 figures 1 21145 block diagram............................................................................................ 3 2 21145 176-pin pinout diagram (top view) ........................................................... 4 3 21145 144-pin pinout diagram (top view) ........................................................... 5 4 pci and cardbus clock specification timing diagram ...................................... 21 5 timing diagram for other pci and cardbus signals.......................................... 22 6 receiver data symbol signal mask...................................................................... 24 7 internal sia mode 10base-t interface timing diagramtransmit .................. 26 8 internal sia mode 10base-t interface timing diagramreceive ................... 27 9 internal sia mode 10base-t interface timing diagramidle link pulse ......... 28 10 mii/sym port timing diagramtransmit........................................................... 29 11 mii/sym port timing diagramreceive ............................................................ 30 12 sym port timing diagramsignal detect ......................................................... 31 13 mii port timing diagramreceive error............................................................ 32 14 mii port timing diagramcarrier sense and collision...................................... 32 15 expansion rom read timing diagram .............................................................. 33 16 expansion rom write timing diagram .............................................................. 34 17 serial rom port timing diagram........................................................................ 35 18 external register read timing diagram............................................................. 36 19 external register write timing diagram............................................................. 36 20 write access timing ........................................................................................... 37 21 read access timing ........................................................................................... 38 22 21145 package marking ..................................................................................... 39 23 176-pin tqfp package ...................................................................................... 40 24 144-pin tqfp package ...................................................................................... 41 tables 1 functional description of 21145 signals............................................................... 6 2 input pins (sheet 1 of 2) .................................................................................... 13 3 output pins ......................................................................................................... 14 4 input/output pins ................................................................................................ 15 5 open drain pins.................................................................................................. 15 6 signal functions.................................................................................................. 16 7 voltage limit ratings .......................................................................................... 18 8 temperature limit ratings.................................................................................. 18 9 crystal oscillator specification............................................................................ 19 10 21145 power specifications (25 mhz) ................................................................ 19 11 21145 power specifications (33 mhz) ................................................................ 19 12 i/o voltage specifications for 5 v levels ............................................................ 20 13 i/o voltage specifications for 3.3 v levels ......................................................... 20 14 reset timing parameters .................................................................................. 20 15 pci and cardbus clock timing specifications ................................................... 21 preliminary datasheet v 21145 16 other pci and cardbus signals timing specifications......................................22 17 homepna transmit timing parameters .............................................................23 18 transmit pad dc specifications...........................................................................23 19 homepna receive ac electrical characteristics ...............................................24 20 twisted-pair dc specifications (sheet 1 of 2) ...................................................24 21 internal sia mode 10base-t interface timing specificationstransmit ..........26 22 internal sia mode 10base-t interface timing specificationsreceive ...........27 23 internal sia mode 10base-t interface timing specificationsidle link pulse.28 24 mii interface ......................................................................................................28 25 mii/sym port timing limitstransmit .............................................................29 26 mii/sym port timing limitsreceive ..............................................................30 27 sym port timing limitssignal detect..............................................................31 28 mii port timing limitsreceive error ................................................................32 29 mii port timing limitscarrier sense and collision ..........................................32 30 expansion rom and serial rom port dc specifications...................................33 31 expansion rom read timing specifications......................................................34 32 expansion rom write timing specifications......................................................34 33 serial rom port timing characteristics ............................................................35 34 external register timing specifications..............................................................36 35 modem write access timing values...................................................................37 36 modem read access timing values ..................................................................38 37 21145 identifiers..................................................................................................39 38 144-pin lqfp package dimensions...................................................................42 21145 preliminary datasheet 1 1.0 introduction this manual contains detailed electrical and mechanical specifications for the 21145 phoneline/ ethernet lan controller. 1.1 manual organization this manual contains the following. ? section 1.0 , introduction, provides a general description of the 21145 and an overview of the hardware components. ? section 2.0 pinout and signal descriptions, provides the physical layout of the 21145 and describes each of the input and output signals. ? section 3.0 electrical and environmental specifications, describes the 21145s electrical and environmental specifications. ? section 4.0 mechanical specifications, includes the 21145 144-pin and 176-pin package marking and mechanical specifications. 1.2 general description the 21145 is an ethernet/homepna lan controller for both 100 mb/s and 10 mb/s data rates, that integrates a homepna phy for 1 mb/s data rate home networking on telephone lines. the 21145 provides a direct interface to the peripheral component interconnect (pci) local bus or to the cardbus. the 21145 interfaces to the host processor by using onchip command and status registers (csrs) and a shared host memory area, set up mainly during initialization. this minimizes processor involvement in the 21145 operation during normal reception and transmission. the 21145 also incorporates a modem interface, and can operate with a wide range of modem chipsets available in the marketplace. the 21145 is optimized for low power pci/cardbus based systems and supports a power-management mechanism based upon the onnow architecture for microsofts pc 97 hardware design guide, pc 98 hardware design guide, and pc 99 hardware design guide . large fifos allow the 21145 to efficiently operate in systems with longer latency periods. bus traffic is also minimized by filtering out received runt frames and by automatically retransmitting collided frames without a repeated fetch from the host memory. the 21145 provides an upgradable expansion rom interface. the 21145 provides these network interfaces: ? 10base-t 10 mb/s port ? homepna port ? a media-independent/symbol interface (mii/sym) 10/100 mb/s port the 10base-t port provides a direct ethernet connection to the twisted-pair (tp) interface. the homepna port provides a direct interface to a telephone line at a rate of 1 mb/s. 21145 2 preliminary datasheet the mii/sym port supports two operational modes: ? mii modea full implementation of the mii standard ? sym modesymbol interface to an external 100 mb/s front-end decoder (endec). in this mode the 21145 uses an onchip physical coding sublayer (pcs) and a scrambler/descrambler circuit to enable a low-cost 100base-t implementation. the 21145 is capable of functioning in a full-duplex environment for the mii/sym and 10base-t ports. 1.3 21145 block diagram the following list describes the 21145 hardware components, and figure 1 shows a block diagram of the 21145: ? pci/cardbus interfaceincludes all interface functions to the pci and cardbus bus. handles all interconnect control signals; and executes dma and i/o transactions. ? boot rom/modem portprovides an interface to perform read and write operations to isa compliant modem chipsets and to the boot rom; supports accesses to bytes or longwords (32- bit) to the boot rom. provides the ability to connect an external 8-bit register to the boot rom port. ? serial rom portprovides a direct interface to a microwire rom for storage of the ethernet address and system parameters. ? general-purpose registerenables software use for input or output functions and leds. ? dmacontains independent receive and transmit controllers; handles data transfers between cpu memory and onchip memory. ? fifoscontains independent fifos for receive and transmit. supports automatic packet deletion on receive (runt packets or after a collision) and packet retransmission after a collision on transmit. ? rxmhandles all csma/cd 1 receive operations, and transfers the network data from the endec to the receive fifo. ? txmhandles all csma/cd mac 2 transmit operations, and transfers data from transmit fifo to the endec for transmission. ? sia interfaceperforms 10 mb/s physical layer network operations; implements the homepna and 10base-t functions, including the manchester encoder and decoder functions. ? nwayimplements the ieee 802.3 auto-negotiation algorithm. ? physical coding sublayerimplements the encoding and decoding sublayer of the 100base- tx (cat5) specification, including the squelch feature. ? homepna phyimplements the homepna telephone network interface. ? scrambler/descramblerimplements the twisted-pair physical layer medium dependent (tp-pmd) scrambler/descrambler scheme for 100base-tx. 1. carrier-sense multiple access with collision detection. 2. media access control. 21145 preliminary datasheet 3 ? three network interfacesa homepna interface, a 10base-t interface, and an mii/sym interface provide a full mii signal interface and direct interface to the 100 mb/s endec for cat5. ? wake-up-controllerenables power-management control compliant with the acpi. figure 1. 21145 block diagram a5991-01 boot rom and modem and external register serial rom board control and leds 32 16 16 4 1 1 1 32 32 4 32 32 pci/card bus boot rom/ modem port serial rom port general purpose register wake-up controller physical coding sublayer (pcs) scrambler/ descrabler mii/sym interface 10base-t interface 10 mb/s 10/100 mb/s residential telephone line homepna phy nway sia interface pci/cardbus interface dma rx fifo rxm txm tx fifo 4 4 4 21145 4 preliminary datasheet 2.0 pinout and signal descriptions this section describes the 21145 pinouts and signals. 2.1 21145 pinout the 21145 is offered as a 176-pin lqfp or a 144-pin lqfp. figure 2 and figure 3 show the 176-pin and 144-pin device pinouts respectively. figure 2. 21145 176-pin pinout diagram (top view) a5990-01 44 iref vdd xtal1 xtal2 vss gep<3>/link gep<2>rcv_match/wake gep<1>/activ gep<0> mdm_a<2> mdm_a<1> mdm_a<0> mdm_chip_sel br_ad<7>/mdm<7> br_ad<6>/mdm<6> vss br_ad<5>/mdm<5> br_ad<4>/mdm<4> vdd vss br_ad<3>/mdm<3> br_ad<2>/mdm<2> vss clkrun_l ad<0> ad<1> vss ad<2> ad<3> vss vss mii/sym_tclk mii_crs/sd rsv mdm_int mdm_a<3> vss mdm_a<4> vss hr_rx_n hr_rx_p vdd rsv rsv rsv vss vdd mii_mdio mii_mdc mii/sym_rxd<3> mii/sym_rxd<2> mii/sym_rxd<1> mii/sym_rxd<0> mii_dv mii_sym_rclk mii_rx_err/sel10_100 vss vdd vss vss vdd vdd c_be_l<1> ad<15> ad<14> mdm_pwr_down ad<13> vss vdd vss ad<23> ad<22> ad<21> vss ad<20> ad<19> ad<18> vdd rsv_vdd ad<17> ad<16> c_be_l<2> frame_l irdy_l trdy_l vss rsv vss mdm_spkr_en 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 31 32 33 34 35 36 132 131 130 129 128 127 126 125 124 122 123 121 120 119 118 117 116 115 114 113 112 111 110 109 102 101 100 99 98 97 7 5 7 6 7 7 7 8 4 6 4 8 4 9 5 0 5 1 5 2 5 35 46789012 5 555556666 3 6 4 6 5 6 6 6 7 6 8 7 9 8 0 4 7 1 6 6 1 5 5 1 5 4 1 5 3 1 4 6 1 4 5 1 4 4 1 4 2 1 4 1 1 4 3 1 7 6 1 7 5 1 7 4 1 7 3 1 7 2 1 7 1 1 7 0 1 6 9 1 6 8 1 6 7 1 6 5 1 6 4 1 6 3 1 6 2 1 6 1 1 6 0 1 5 9 1 5 8 1 5 7 1 5 6 21145 br_ad<1>/mdm<1> br_ad<0>/mdm<0> br_a<1>/mdm_rd br_a<0>/cb_pads_l/mdm_wr br_ce_l vss tp_td+ int_l vdd vdd vss tp_td-- tp_td- tp_td++ vdd tp_rd+ hr_txp tp_rd- hr_txn hr_txph hr_txnh rsv rsv rsv mdm_ring_ind vss vss rst_l vss vss ad<31> ad<30> ad<29> vdd ad<28> ad<27> vdd vdd pci_clk vdd_clamp gnt_l req_l 25 26 27 28 29 30 108 107 106 105 104 103 mii_txen/sym_txd<4> mii/sym_txd<0> mii/sym_txd<1> mii/sym_txd<3> mii_col/sym_rxd<4> mii/sym_txd<2> devsel_l mdm_rst stop_l serr_l par perr_l 6 9 7 0 7 1 7 2 7 3 7 4 1 5 2 1 5 1 1 5 0 1 4 8 1 4 7 1 4 9 sr_ck sr_di sr_do vcap_h vddac vddac 1 3 8 1 3 7 1 3 6 1 3 4 1 3 3 1 3 5 vss sr_cs 1 4 0 1 3 9 ad<5> ad<6> ad<7> c_be_l<0> vss vdd 94 93 92 91 90 89 ad<4> vdd 96 95 vdd ad<10> ad<9> vss vdd ad<8> 8 3 8 4 8 5 8 6 8 7 8 8 ad<12> ad<11> 8 1 8 2 39 40 41 42 43 ad<25> ad<24> c_be_l<3> idsel vss vdd ad<26> vss 37 38 4 5 vdd 21145 preliminary datasheet 5 2.2 signal descriptions the following terms describe the 21145 pinout used in table 1 : ? address phase address and appropriate bus commands are driven during this cycle. ? data phase data and the appropriate byte enable codes are driven during this cycle. ? _l all pin names with the _l suffix are active low. the following abbreviations are used in table 1 : o = output i/o = input/output o/d = open drain figure 3. 21145 144-pin pinout diagram (top view) a6439-01 iref xtal1 xtal2 vss gep<3>/link gep<2>rcv_match/wake gep<1>/activ gep<0> rsv rsv rsv rsv vdd vss rsv rsv vss rsv rsv rsv cb_pads_l clkrun_l vdd ad<5> ad<6> ad<7> c_be_|<0> vss vdd mii /sym_t clk mii_crs/sd vss hr_rx_n hr_rx_p vdd rsv rsv rsv vss vdd mii_mdio mii_mdc mii/sym_rxd<3> mii/sym_rxd<2> mii/sym_rxd<1> mii/sym_rxd<0> mii_dv mii/sym_rclk mii_rx_err/sel10_100 vss vdd vss vdd devsel_l c_be_l<1> ad<15> ad<14> ad<13> vss vdd vss ad<23> ad<22> ad<21> vss ad<20> ad<19> ad<18> vdd ad<17> ad<16> c_be_l<2> frame_l irdy_l trdy_l 1 2 3 4 5 6 7 8 9 11 10 12 13 14 15 16 17 18 19 20 21 22 23 24 31 32 33 34 35 36 108 107 106 105 104 103 102 101 100 98 99 97 96 95 94 93 92 91 90 89 88 87 86 85 78 77 76 75 74 73 21145 ad<0> ad<1> vss ad<2> ad<3> ad<4> tp_td+ int_l vdd vdd vss tp_td-- tp_td- tp_td++ vdd tp_rd+ hr_txp tp_rd- hr_txn hr_txph hr_txnh rst_l vss vdd ad<31> ad<30> ad<29> vdd ad<28> ad<27> vss ad<25> ad<24> c_be_|<3> idsel vss vdd ad<26> pci_clk vdd_clamp gnt_l req_l 25 26 27 28 29 30 84 83 82 81 80 79 mii_txen/sym_txd<4> mii/sym_txd<0> mii/sym_txd<1> mii/sym_txd<3> mii_col/sym_rxd<4> mii/sym_txd<2> stop_l serr_l par perr_l sr_ck sr_di sr_do vcap_h vddac vddac vss sr_cs vdd ad<10> ad<9> vss vdd ad<8> ad<12> ad<11> 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 vdd 21145 6 preliminary datasheet p = power pins labeled rsv are reserved for future use and must be left unconnected. the following signals have an internal pull-up: sr_do mii/sym_tclk signal sr_cs has an internal pull-down. table 1 provides a functional description of each of the 21145 signals. these signals are listed alphabetically. table 1. functional description of 21145 signals (sheet 1 of 8) signal type pin number, 176-pin pin number, 144-pin description ad<31:0> i/o 31, 32, 33, 35, 36, 37, 39, 40, 47, 48, 49, 51, 52, 53, 56, 57, 76, 77, 80, 81, 82, 84, 85, 86, 92, 93, 94, 96, 97, 98, 100, 101 23, 24, 25, 27, 28, 29, 31, 32, 39, 40, 41, 43, 44, 45, 47, 48, 61, 62, 64, 65, 66, 68, 69, 70, 76, 77, 78, 80, 81, 82, 84, 85 32-bit pci address and data lines. address and data bits are multiplexed on the same pins. during the first clock cycle of a transaction, the address bits contain a physical address (32 bits). during subsequent clock cycles, these same lines contain 32 bits of data. a 21145 bus transaction consists of an address phase followed by one or more data phases. the 21145 supports both read and write bursts (in master operation mode only). little and big endian byte ordering can be used. br_a<0>/cb_pads_l/ mdm_wr (on 176 pins) br_a<0>/cb_pads_l (on 144 pins) i/o 105 87 for the 176-pin 21145 only : during operation, when accessing the modem chipset (mdm_chip_sel is asserted), this pin is used as the modem write line and is active low. when the modem is not accessed (mdm_chip_sel is deasserted), this pin is used as the expansion rom address line bit 0. in a 256kb configuration, this pin also carries in two consecutive address cycles, expansion rom address bits 16 and 17. for both the 144-pin and 176-pin 21145 : during reset, this pin also determines the type of signals to use for the pci/cardbus output pins, either pci or cardbus. by default, this pin selects pci signaling. to select cardbus signaling, this pin must be connected to a pull-down resistor. br_a<1>/mdm_rd o 106 na for the 176-pin 21145 only : during operation, when accessing the modem chipset (mdm_chip_sel is asserted), this pin is used as the modem read line and is active low. when the modem is not accessed (mdm_chip_sel is deasserted), this pin is used as the expansion rom address line bit 1. this pin also latches the expansion rom address and control lines by the two external latches. 21145 preliminary datasheet 7 br_ad<7:0>/ 21145 8 preliminary datasheet gep<2> / rcv_match/ wake i/o 125 102 this pin can be configured by software to be: ? a general-purpose pin that performs either input or output functions. ? a status pin that provides an led that indicates a receive packet has passed address recognition. this pin can also be controlled by pme_enable bit (func0_hwoptions<3>) in the serial rom to be a wake- up event pin that can be connected to pin pme# of the pci connector or pin cstschg of the cardbus connector. when this pin is in a wake function, bit mischwoptions<1> in the serial rom determines the polarity. gep<3>/link i/o 126 103 this pin can be configured by software to be: ? a general-purpose pin that performs either input or output functions. ? a status pin that provides an led to indicate (according to the mischwoptions<0> field in the serial rom): network link integrity state for 10base-t or 100base-tx. both network activity and network link integrity state. ? an input link status pin for onnow support. when used with an mii phy device, this pin should be connected to the mii phy link indication pin (the 21145 interprets a high logic level on this pin as link- pass). this pin should not be left unconnected if it is used as an input in the d1, d2, or d3 power states. gnt_l i 29 21 bus grant asserts to indicate to the 21145 that access to the bus is granted. hr_rx_n i 175 143 homepna negative differential receive input from the phone line. hr_rx_p i 174 142 homepna positive differential receive input from the phone line. hr_txn o 12 12 homepna negative differential transmit output to phone line. hr_txnh o 14 14 homepna high power negative differential transmit output to phone line. hr_txp o 11 11 homepna positive differential transmit output to phone line. hr_txph o 13 13 homepna high power positive differential transmit output to phone line. idsel i 42 34 initialization device select asserts to indicate that the host is issuing a configuration cycle to the 21145. table 1. functional description of 21145 signals (sheet 3 of 8) signal type pin number, 176-pin pin number, 144-pin description 21145 preliminary datasheet 9 int_l o/d 21 15 interrupt request asserts when one of the appropriate bits of csr5 sets and causes an interrupt, provided that the corresponding mask bit in csr7 is not asserted. interrupt request deasserts by writing a 1 into the appropriate csr5 bit. if more than one interrupt bit is asserted in csr5 and the host does not clear all input bits, the 21145 deasserts int_l for one cycle to support edge-triggered systems. iref i 132 108 current reference input for the analog phase-locked loop logic. irdy_l i/o 60 51 initiator ready indicates the bus masters ability to complete the current data phase of the transaction. a data phase is completed on any rising edge of the clock when both irdy_l and target ready trdy_l are asserted. wait cycles are inserted until both irdy_l and trdy_l are asserted together. when the 21145 is the bus master, it asserts irdy_l during write operations to indicate that valid data is present on the 32-bit ad lines. during read operations, the 21145 asserts irdy_l to indicate that it is ready to accept data. mdm_a<4:0> o 120, 121, 122, 142, 143 na modem address lines. address lines that are not needed in order to access the modem should be left unconnected. for example, if the modem chipset has only 8 registers, mdm_a<4:3> should be left unconnected. mdm_chip_sel o 119 na modem chip select. this pin is active low. mdm_int i 144 na modem interrupt line. when asserted, the 21145 asserts the int_l pin. this pin is active high. it must be connected to a pull-down resistor. mdm_pwr_down o 79 na modem power down. this pin is asserted when the modem function is in d3 power state. it can be used by the modem chipset power control. the polarity of this pin is determined by the func1_hwoptions<5> bit in the serial rom. mdm_ring_ind i 18 na modem ring indicator. the assertion of this pin affects the assertion of the wake pin. the polarity of this pin is determined by the func1_hwoptions<4> bit in the serial rom. this pin must not be left floating. mdm_rst o 70 na modem reset. this pin is asserted for 15 m s from the end of the 21145s power-up reset pulse, and on moving from the d3 to the d0 power state. mdm_spkr_en o 65 na modem speaker enable. this pin reflects the audio enable bits of the modem function status changed registers. if the func1_hwoptions<7> bit in the serial rom is set, the value of the femr<5> is driven on the mdm_spkr_en pin. if the func1_hwoptions<7> is cleared, the value of femr<6> is driven on the mdm_spkr_en pin. table 1. functional description of 21145 signals (sheet 4 of 8) signal type pin number, 176-pin pin number, 144-pin description 21145 10 preliminary datasheet mii_clsn/sym_rxd<4> i 147 118 in mii mode (csr6<18>=1, csr6<23>=0), this pin functions as the collision detect. when the external physical layer protocol (phy) device detects a collision, it asserts this pin. in sym mode (csr6<18>=1, csr6<23>=1), this pin functions as receive data. this line along with the four receive lines (sym_rxd<3:0>) provides five parallel data lines in symbol form. this data is controlled by an external physical layer medium-dependent (pmd) device and should be synchronized to the sym_rclk signal. mii_crs/sd i 146 117 in mii mode this pin functions as the carrier sense and is asserted by the phy when the media is active. in sym mode this pin functions as the signal detect indication. it is controlled by an external pmd device. if no phy device is connected to the mii/sym port, the mii_crs/sd pin should be tied to vss in order to make the link-integrity test function properly. mii_dv i 161 129 data valid is asserted by an external phy when receive data is present on the mii_rxd lines and is deasserted at the end of the packet. this signal should be synchronized with the mii_rclk signal. mii_mdc o 166 134 mii management data clock is sourced by the 21145 to the mii phy device as a timing reference for the transfer of information on the mii_mdio signal. mii_mdio i/o 167 135 mii management data input/output transfers control information and status between the phy and the 21145. this signal should be tied to an external pullup resistor if an mii phy is connected, and to an external pulldown resistor otherwise. mii/sym_rclk i 160 128 supports either the 25-mhz or 2.5-mhz receive clock. this clock is recovered by the phy. mii_rx_err/sel10_100 i/o 159 127 when used with an mii phy device (csr6<18>=1, csr6<23>=0), this pin functions as receive error input. it is asserted when a data decoding error is detected by an external phy device. this signal is synchronized to mii_rclk and can be asserted for a minimum of one receive clock. when asserted during a packet reception, it sets the cyclic redundancy check (crc) error bit in the receive descriptor (rdes0). when used with a sym phy device (csr6<23>=1), this pin functions as select 10/100 output. the signal sel10_100 equals 1 when the 21145 is in 100-mb/s sym mode (csr6<18>=1) and equals 0 when the 21145 is in 10base-t mode (csr6<18>=0). mii/sym_rxd<3:0> i 162, 163, 164, 165 130,131, 132,133, four parallel receive data lines. this data is driven by an external phy that attached the media and should be synchronized with the mii_rclk signal. mii/sym_tclk i 153 124 supports the 25-mhz or 2.5-mhz transmit clock supplied by the external pmd device. this clock should always be active. table 1. functional description of 21145 signals (sheet 5 of 8) signal type pin number, 176-pin pin number, 144-pin description 21145 preliminary datasheet 11 mii/sym_txd<3:0> o 148, 149, 150, 151 119, 120, 121, 122 four parallel transmit data lines. this data is synchronized to the assertion of the mii_tclk signal and is latched by the external phy on the rising edge of the mii_tclk signal. mii_txen/sym_txd<4> o 152 123 in mii mode, this pin functions as transmit enable. it indicates that a transmission is active on the mii port to an external phy device. in sym mode, this pin functions as transmit data. this line along with the four data transmit lines (sym_txd<3:0>) provides five parallel data lines in symbol form. the data is synchronized to the rising edge of the sym_tclk signal. par i/o 74 59 parity is calculated by the 21145 as an even parity bit for the 32-bit ad and 4-bit c_be_l lines. during address and data phases, parity is calculated on all the ad and c_be_l lines whether or not any of these lines carry meaningful information. pci_clk i 27 19 the clock provides the timing for the 21145 related pci bus transactions. all the bus signals are sampled on the rising edge of pci_clk. the supported clock frequency range is 20 mhz to 33 mhz. perr_l i/o 72 57 parity error asserts when a data parity error is detected. when the 21145 is the bus master and a parity error is detected, the 21145 asserts both csr5 bit 13 (fatal bus error) and cfcs bit 24 (data parity report). next, it completes the current data burst transaction, then stops operation. after the host clears the system error via csr5<13>, the 21145 continues its operation. the 21145 asserts perr_l when a data parity error is detected in either a master-read or a slave-write operation. req_l o 30 22 bus request is asserted by the 21145 to indicate to the bus arbiter that it wants to use the bus. rst_l i 22 16 resets the 21145 to its initial state. this signal must be asserted for at least 10 active pci clock cycles. when in the reset state, all pci output pins are put into tristate and all pci o/d signals are floated. rsv 15, 16, 17, 63, 145, 170, 171, 172 88, 89, 90, 92, 93, 96, 97, 98, 99, 138, 139, 140 reserved. these pins should remain unconnected. rsv_vdd i 55 na must be connected to vdd for proper operation. serr_l o/d 73 58 if an address parity error is detected and cfcs bit 8 (serr_l enable) is enabled, 21145 asserts both serr_l (system error) and cfcs bit 30 (signal system error). when an address parity error is detected, system error asserts two clocks after the failing address. sr_ck o 138 114 serial rom clock signal. this pin provides a serial clock output for the serial rom. sr_cs o 139 115 serial rom chip-select signal. this pin provides a chip select for the serial rom. table 1. functional description of 21145 signals (sheet 6 of 8) signal type pin number, 176-pin pin number, 144-pin description 21145 12 preliminary datasheet sr_di o 137 113 serial rom data-in signal. this pin serially shifts the write data from the 21145 to the serial rom device. sr_do i 136 112 serial rom data-out signal. this pin serially shifts the read data from the serial rom device to the 21145. stop_l i/o 71 56 stop indicator indicates that the current target is requesting the bus master to stop the current transaction. the 21145 responds to the assertion of stop_l when it is the bus master, either to disconnect, retry, or abort. tp_rdC i 10 10 twisted-pair negative differential receive data from the twisted-pair lines. tp_rd+ i 9 9 twisted-pair positive differential receive data from the twisted-pair lines. tp_tdC tp_tdC C o o 5 4 5 4 twisted-pair negative differential transmit data. the positive and negative differential transmit data outputs are combined resistively outside the 21145 with equalization to compensate for intersymbol interference on the twisted-pair medium. tp_td+ tp_td+ + o o 6 7 6 7 twisted-pair positive differential transmit data. the positive and negative differential transmit data outputs are combined resistively outside the 21145 with equalization to compensate for intersymbol interference on the twisted-pair medium. trdy_l i/o 61 52 target ready indicates the target agents ability to complete the current data phase of the transaction. a data phase is completed on any clock when both trdy_l and irdy_l are asserted. wait cycles are inserted until both irdy_l and trdy_l are asserted together. when the 21145 is the bus master, target ready is asserted by the bus slave on the read operation, which indicates that valid data is present on the ad lines. during a write cycle, it indicates that the target is prepared to accept data. vcap_h i 134 110 capacitor input for analog phase-locked loop logic. vdd p 1, 2, 8, 25, 26, 34, 44, 45, 54, 67, 68, 83, 88, 89, 95, 113, 130, 131, 157, 168, 173 1, 2, 8, 18, 26, 36, 37, 46, 54, 67, 72, 73, 79, 95, 107, 125, 136, 141 3.3-v supply input. these pins should be connected to the auxiliary power, if such power exists. otherwise, these pins should be connected to the main power. vddac p 133, 135 109,111 supplies +3.3-v input for analog phase-locked loop logic. these pins should each be decoupled with a separate 0.1 f capacitor to ground. the capacitors should be located as close to the package pins as possible. vdd_clamp p 28 20 supplies +5-v or +3.3-v reference for clamp logic. this pin is also used to determine the lack of main power when the auxiliary power is on. it should be connected to the main power. this pin determines whether 5 v or 3.3 v signalling is used on the pci bus. table 1. functional description of 21145 signals (sheet 7 of 8) signal type pin number, 176-pin pin number, 144-pin description 21145 preliminary datasheet 13 2.3 pin tables this section contains four types of pin tables: ? table 2 lists the input pins. ? table 3 lists the output pins. ? table 4 lists the input/output pins. ? table 5 lists the open drain pins. vss p 3, 19, 20, 23, 24, 38, 43, 46, 50, 62, 64, 66, 78, 87, 90, 99, 103, 109, 112, 116, 127, 140, 141, 154, 155, 156, 158, 169, 176 3, 17, 30, 35, 38, 42, 53, 63, 71, 74, 83, 91, 94, 104, 116, 126, 137, 144 ground pins. xtal1 i 129 106 20-mhz crystal input, or crystal oscillator input. this input should always be active. xtal2 o 128 105 crystal feedback output pin used for crystal connections only. if this pin is unused, then it should be unconnected. table 1. functional description of 21145 signals (sheet 8 of 8) signal type pin number, 176-pin pin number, 144-pin description table 2. input pins (sheet 1 of 2) signal active level hr_rx_n analog hr_rx_p analog gnt_l low idsel high iref mdm_int high mdm_ring_ind dependent on func1_hwoptions<4> in the serial rom. mii_clsn/sym_rxd<4> high for mii_clsn, na for sym_rxd<4>. mii_crs/sd high mii_dv high mii/sym_rclk mii/sym_rxd<3:0> mii/sym_tclk pci_clk 21145 14 preliminary datasheet rst_l low rsv_vdd sr_do tp_rdC tp_rd+ vcap_h xtal1 table 3. output pins signal active level br_ce_l low hr_txn hr_txnh hr_txp hr_txph mdm_a<4:0> mdm_chip_sel low mdm_pwr_down dependent on func1_hwoptions<5> in the serial rom. mdm_spkr_en high mii_mdc mii/sym_txd<3:0> mii_txen/sym_txd<4> high for mii_txen, low for sym_txd<4>. req_l low sr_ck sr_cs high sr_di tp_tdC tp_tdC C tp_td+ tp_td+ + xtal2 table 2. input pins (sheet 2 of 2) signal active level 21145 preliminary datasheet 15 table 4. input/output pins signal active level ad<31:0> br_a<0>/cb_pads_l high for br_a<0>, low for cb_pads_l. br_ad<7:0> clkrun_l low c_be_l<3:0> low devsel_l low frame_l low gep<0> gep<1>/activ na for gep<1>, high for activ. gep<2>/rcv_match/wake na for gep<2>, high for rcv_match, controlled by bit mischwoptions<1> (pme_stschg) in the serial rom for wake. tristate when not used as wake. gep<3>/link na for gep<3>, high for link. irdy_l low mii_mdio mii_rx_err/sel10_100 high for mii_rx_err, na for sel10_100. par high perr_l low stop_l low trdy_l low table 5. open drain pins signal active level clkrun_l low int_l low serr_l low wake controlled by bit mischwoptions<1> (pme_stschg) in the serial rom. 21145 16 preliminary datasheet 2.4 signal grouping by function table 6 lists the signals according to their interface function. table 6. signal functions (sheet 1 of 2) interface function signals pci/cardbus address and data ad<31:0>, par arbitration gnt_l, req_l bus command and byte enable c_be_l<3:0> device select devsel_l, idsel error reporting perr_l, serr_l interrupt int_l system pci_clk, rst_l control signals frame_l, stop_l, irdy_l, trdy_l power-management status wake clock status clkrun_l pad select cb_pads_l modem connections (176-pin 21145 only) address lines mdm_a<4:0> data lines mdm<7:0> chip select mdm_chip_sel read line mdm_rd write line mdm_wr interrupt mdm_int power down mdm_pwr_down reset mdm_rst ring indicator mdm_ring_ind speaker enable mdm_spkr_en mii/sym network port transmit data lines mii/sym_txd<3:0> receive data lines mii/sym_rxd<3:0> transmit, receive clocks mii/sym_tclk, mii/sym_rclk transmit enable mii_txen collision detect mii_clsn mii error reporting mii_rx_err data control mii_dv, mii_crs mii management data clock mii_mdc mii management data input/output mii_mdio signal detection sd sym mode data lines sym_rxd<4>, sym_txd<4> sym mode 10/100 select sel10_100 serial rom port serial rom sr_ck, sr_cs, sr_di, sr_do expansion port (176-pin 21145 only) rom interface br_a<1:0>, br_ad<7:0> 21145 preliminary datasheet 17 power 3.3-v or 5.0-v supply input vdd_clamp 3.3-v supply input vdd, vddac ground vss general-purpose port and leds general-purpose pins gep<3:0> led indicators activ, rcv_match, link network connection analog phase-locked loop logic iref, vcap_h crystal oscillator xtal1, xtal2 twisted-pair transmit and receive data tp_rdC, tp_rd+, tp_tdC, tp_tdC C, tp_td+, tp_td+ + homepna port connect to phone line hr_txp, hr_txn, hr_txph, hr_txnh, hr_rx_p, hr_rx_n table 6. signal functions (sheet 2 of 2) interface function signals 21145 18 preliminary datasheet 3.0 electrical and environmental specifications this section contains the electrical and environmental specifications for the 21145. caution: stresses greater than the maximum or less than the minimum ratings can cause permanent damage to the 21145. exposure to the maximum or minimum ratings for extended periods of time lessen the reliability of the 21145. 3.1 voltage limit ratings table 7 lists the voltage limit ratings. 3.2 temperature limit ratings table 8 lists the temperature limit ratings. 3.3 oscillator characteristics when driving the 21145s integrated oscillator circuitry from an external clock source, an external clock having the following characteristics must be used to ensure proper operation of the 21145: ? clock frequency: 20 mhz 0.01% (100 ppm, ttl, or cmos) ? rise/fall time: < 4 ns ? duty cycle: 40%C60% table 7. voltage limit ratings parameter minimum maximum power supply voltage 3.0 v 3.6 v vdd_clamp (5 v) 4.75 v 5.25 v vdd_clamp (3.3 v) 1 3 v 3.6 v esd protection voltage 2 2000 v note: 1. in the 3.3 v signaling environment, vdd_clamp must not be greater than vdd + 0.3 v. 2. using the hbm (human body modulation) model. table 8. temperature limit ratings parameter minimum maximum storage temperature C55 c +125 c operating temperature 0 c +70 c 21145 preliminary datasheet 19 table 9 lists the specifications for the crystal oscillator. 3.4 power specifications this section describes the power specifications for all versions of the 21145 device. 3.4.1 21145 power specifications the values in table 10 are based on a pci or cardbus clock frequency of 25 mhz, vdd at 3.6 v, ta at 0 c, and a network data rate of 100 mb/s. the values in table 11 are typical values based on a pci or cardbus clock frequency of 33 mhz, vdd at 3.3 v, room temperature, and a network data rate of 1 mb/s in the homepna port. table 9. crystal oscillator specification category value frequency 20 mhz tolerance 0.01% at 25 c (100 ppm) stability 0.005% at 0 c to 70 c (100 ppm) table 10. 21145 power specifications (25 mhz) condition idd (ma) d0 in normal mode, full network activity 267 d0 in snooze mode, 50% network activity 274 d1 in snooze mode, 50% network activity 206 d2 in snooze mode, 50% network activity 200 d3 in snooze mode, no network activity 1 185 after power-up 2,3 200 1. pci/cardbus clock stopped. 2. using the cardbus pads. 3. after power-up, the 21145 initializes to sleep mode. table 11. 21145 power specifications (33 mhz) condition idd (ma) d0 in normal mode, full network activity 190 d0 in snooze mode, 50% network activity 185 d1 in snooze mode, 50% network activity 150 d2 in snooze mode, 50% network activity 150 d3 in snooze mode, no network activity 1 135 1. pci/cardbus clock stopped. 21145 20 preliminary datasheet 3.5 pci bus and cardbus electrical parameters this section describes the pci bus and cardbus characteristics for the 21145. 3.5.1 pci and cardbus i/o voltage specifications the 21145 meets the i/o voltage specifications listed in table 12 and table 13 . 3.5.2 system bus reset system bus (pci or cardbus) reset (rst_l) is an asynchronous signal that must be active for at least 10 system bus (pci or cardbus) clock (pci_clk) cycles. table 14 lists the reset signal limits. 3.5.3 pci and cardbus clock specifications the clock frequency range 1 for pci and cardbus is between 20 mhz and 33 mhz. figure 4 shows the pci and cardbus clock specification timing characteristics and the required measurement points for both the 5 v and 3.3 v signaling environments. table 15 lists the frequency-derived clock specifications. table 12. i/o voltage specifications for 5 v levels symbol parameter condition minimum maximum v ih input high voltage 2 v vdd_clamp + 0.5 v v il input low voltage C0.5 v 0.8 v i i 1 input leakage current 0.5 v 21145 22 preliminary datasheet figure 5. timing diagram for other pci and cardbus signals table 16. other pci and cardbus signals timing specifications symbol parameter minimum typical maximum t val 1 clk-to-signal valid delay 2 2 ns 11 ns t val 1 clk-to-signal valid delay 3 2 ns 18 ns t on float-to-active delay from clk 2 ns t off active-to-float delay from clk 28 ns t su input signal valid setup time before clk 7 ns t h input signal hold time from clk 0 ns notes: 1. load for this measurement is as specified in pci local bus specification, revision 2.0 and pci local bus specification , revision 2.1. 2. valid delays for pci, selected by default when pin cb_pad_l is not pulled down externally. 3. valid delays for cardbus, selected when pin cb_pad_l is pulled down externally. a6443-01 clk output input 1 vtest is 1.5 v in a 5.0-v signaling environment and is 0.4 * vdd_clamp in a 3.3-v signaling environment. vtest 1 t val (max) t off t on t h t su t val (min) 21145 preliminary datasheet 23 3.6 homepna specifications 3.6.1 homepna transmit timing parameters (25 c) table 17 describes the homepna transmit timing parameters. 3.6.2 homepna transmit specifications table 18 gives the homepna transmit pads dc specifications. 3.6.3 homepna receive specifications the receiver detects differential input signals between hr_rx_p and hr_rx_n that meet the waveform mask of figure 6 . the mask shows the acceptable limits of the response to a single isolated pulse that meets the homepna phy transmit waveform requirements. the parameters for figure 6 are defined as follows: residual_peak_1 = envelope_peak /10 residual_peak_2 = envelope_peak /20 envelope_peak is defined as the peak level of the waveform arriving during interval a_b in the figure. a representative waveform that meets the mask is shown. the near dc bias is not shown and must include up to +/- 200 v to accommodate pots signaling. the signal must form at least one peak in the shaded portion of the figure bounded between lines a and b. timing in the figure is referenced to the point when the signal first crosses the 5 mv threshold. table 17. homepna transmit timing parameters parameters symbol typical units notes transmit drivers tr/tf hr_txn/p 2 ns 10% to 90% into 100 ohm differential transmit drivers tr/tf hr_txph/nh 2 ns 10% to 90% into 100 ohm differential transmit drivers width hr_txn/p 133 ns transmit drivers width hr_txph/nh 133 ns table 18. transmit pad dc specifications symbol parameter condition minimum maximum units i oh output high current 0.9 vcc 12.5 30 ma i ol output low current 0.1 vcc 26 58 ma 21145 24 preliminary datasheet 3.6.4 homepna receive ac electrical characteristics table 19 describes the receive ac electrical characteristics. figure 6. receiver data symbol signal mask a6444-01 + 2.6 + 6.5 + 13 sec 0 -8 +8 0 mv -tx_peak_v -20% -_residual_peak_1 residual_peak_1 residual_peak_2 -_residual_peak_2 -1mv 1mv tx_peak_v +20% a bcd table 19. homepna receive ac electrical characteristics parameters symbol typical units notes input ac frequency hr_rx_n/hr_rx_p 7.5 mhz input ac voltage hr_rx_n/hr_rx_p 0.01 C 1.4 v differential peak 21145 preliminary datasheet 25 3.7 twisted-pair dc specifications table 20 lists the dc specifications for the twisted-pair parts of the sia. 3.8 serial interface attachment specifications this section describes the dc specifications and timing limits of the sia unit. 3.8.1 internal sia mode 10base-t interface timingtransmit figure 7 shows the internal sia transmit timing characteristics for the 10base-t interface, and table 21 lists the internal sia transmit limits. table 20. twisted-pair dc specifications symbol definition condition minimum typical 1 1. at 3.3 v. maximum unit v toh output high voltage (tp_td and tp_td) i oh = C25 ma 2.5 v v tol output low voltage (tp_td and tp_td) i ol = 25 ma 0.5 v v tsq + differential positive squelch threshold (tp_rd) 300520 mv v tsq C differential negative squelch threshold (tp_rd) C520 C300 mv v tdif differential input voltage range (tp_rd) C3.1 3.1 v 21145 26 preliminary datasheet figure 7. internal sia mode 10base-t interface timing diagramtransmit table 21. internal sia mode 10base-t interface timing specificationstransmit symbol definition minimum maximum unit t pdp tp_td+, tp_tdC propagation delay from xtal1 fall 30 ns t pdr tp_td+, tp_td++, tp_tdC, tp_tdC C rise time 8 ns t pdf tp_td+, tp_td++, tp_tdC, tp_tdC C fall time 8 ns t pdm tp_td+, tp_td++, tp_tdC, tp_tdC C rise and fall time mismatch (not shown) 1 ns t pdc tp_td+ to tp_tdC C and tp_tdC to tp_td++ delay 46 54 ns t ped tp_td end transmit delimiter length 295 355 ns t pen tp_td++/C C end transmit delimiter length 245 305 ns a6447-01 etd (end transmit delimiter) t pdc t pen xtal1 tp_td+ tp_td-- tp_td- tp_td++ t pdr t pdf t pdc t pdp 111 0 t ped 21145 preliminary datasheet 27 3.8.2 internal sia mode 10base-t interface timingreceive figure 8 shows the internal sia receive timing characteristics for the 10base-t interface, and table 22 lists the internal sia receive limits for the 10base-t interface. figure 8. internal sia mode 10base-t interface timing diagramreceive table 22. internal sia mode 10base-t interface timing specificationsreceive symbol definition minimum maximum unit t sn tp_rd start of frame pulse width during smart squelch operation 15 20 ns t sf tp_rd maximum delay between opposite squelch crossings not to turn smart squelch off 140 150 ns t dm tp_rd delay between opposite squelch crossings not recognized as end of packet 140 ns t df tp_rd delay from last squelch crossing recognized as end of packet 150 ns a6448-01 t df t dm t dm t sf t sf t sf t sf t sf t sn t sn t sn tp_rd+/- t sn t sn v tsq+ v tsq- 21145 28 preliminary datasheet 3.8.3 internal sia mode 10base-t interface timingidle link pulse figure 9 shows the internal sia idle link pulse timing characteristics for the 10base-t interface, and table 23 lists the internal sia idle link pulse limits for the 10base-t interface. figure 9. internal sia mode 10base-t interface timing diagramidle link pulse table 23. internal sia mode 10base-t interface timing specificationsidle link pulse symbol definition minimum maximum unit t pld tp_td+ idle link pulse width 80 120 ns t plc tp_td++ and tp_tdC C idle link pulse width 40 60 ns t plp idle link pulse period 8 24 ms a6449-01 t pld t plc t plp t plc tp_td+ tp_td++ tp_td- tp_td-- 21145 preliminary datasheet 29 3.9 mii interface specifications table 24 lists the specifications for the mii interface. 3.10 mii/sym port timing this section describes the mii/sym port timing limits. 3.10.1 mii/sym 10/100 mb/s and 10 mb/s timingtransmit figure 10 shows the mii/sym port transmit timing characteristics, and table 25 lists the mii/sym port transmit timing limits. table 24. mii interface symbol definition condition minimum maximum unit v oh output high voltage i oh = C4 ma 2.4 v v ol output low voltage i ol = 4 ma 0.4 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i in input current v in = vcc or vss C10.0 10.0 m a i oz maximum tristate output leakage current v in = vdd or vss C10.0 10.0 m a figure 10. mii/sym port timing diagramtransmit a6450-01 mii/sym_tclk mii/sym_txd<3:0> mii_txen t cc t ch t val t val t cl t cf t cr 21145 30 preliminary datasheet 3.10.2 mii/sym 10/100 mb/s timingreceive figure 11 shows the mii/sym port receive timing characteristics, and table 26 lists the mii/sym port receive timing limits. table 25. mii/sym port timing limitstransmit symbol definition minimum typical maximum unit t cc 1 mii/sym_tclk cycle 40t 2 ns t ch mii/sym_tclk high time 14t 2 26t 2 ns t cl mii/sym_tclk low time 14t 2 26t 2 ns t cr mii/sym_tclk rise time 8 ns t cf mii/sym_tclk fall time 8 ns t val mii_tclk rise to mii_txen valid time or mii/sym_tclk rise to mii/sym_txd valid time 0 20 ns notes: 1. 50 parts per million. 2. t=1 for 100 mb/s operation; t=10 for 10 mb/s operation. figure 11. mii/sym port timing diagramreceive table 26. mii/sym port timing limitsreceive (sheet 1 of 2) symbol definition minimum typical maximum unit t cc 1 mii/sym_rclk cycle time 40t 2 ns t c mii/sym_rclk high time 14t 2 26t 2 ns t cl mii/sym_rclk low time 14t 2 26t 2 ns t cr mii/sym_rclk rise time 8 ns t cf mii/sym_rclk fall time 8 ns a6451-01 mii/sym_rclk mii/sym_rxd<3:0> mii_dv t cc t ch t ts t th t cl t cf t cr 21145 preliminary datasheet 31 3.10.3 sym 10/100 mb/s timingsignal detect figure 12 shows the sym port signal detect timing characteristics, and table 27 lists the sym port signal detect timing limits. t ts 3 mii/sym_rxd setup (both rise and fall transactions) to mii/sym_rclk rise time or mii_dv setup (both rise and fall transactions) to mii_rclk rise time 8 ns t th mii/sym_rxd hold (both rise and fall transactions) after mii/sym_rclk rise time or mii_dv hold (both rise and fall transactions) after mii_rclk rise time 10 ns notes: 1. 50 parts per million. 2. t=1 for 100 mb/s operation; t=10 for 10 mb/s operation. 3. the receive data (mii/sym_rxd) and data valid (mii_dv) input pins are latched internally on the rising edge of mii/sym_rclk. table 26. mii/sym port timing limitsreceive (sheet 2 of 2) symbol definition minimum typical maximum unit figure 12. sym port timing diagramsignal detect table 27. sym port timing limitssignal detect symbol definition minimum maximum units t ts 1 sd setup (both rise and fall transactions) to sym_rclk fall time 10 ns t th 1 sd hold (both rise and fall transactions) after sym_rclk fall time 12 ns note: 1. input signal detect (sd) is latched internally on the falling edge of sym_rclk. a6452-01 sym_rclk sd t ts t th 21145 32 preliminary datasheet 3.10.4 mii 10/100 mb/s timingreceive error figure 13 shows the mii port receive error timing characteristics, and table 28 lists the mii port receive error timing limits. 3.10.5 mii 10/100 mb/s timingcarrier sense and collision figure 14 shows the mii port carrier sense and collision timing characteristics, and table 29 lists the mii port carrier sense and collision timing limits. figure 13. mii port timing diagramreceive error table 28. mii port timing limitsreceive error symbol definition minimum maximum unit tts 1 mii_rx_err setup (both rise and fall transactions) to mii_rclk rise time 10 ns tth 1 mii_rx_err hold (both rise and fall transactions) after mii_rclk rise time 10 ns note: 1. input signal detect (mii_rx_err) is latched internally on the falling edge of mii_rclk. a6453-01 mii_rclk mii_rx_err t ts t th figure 14. mii port timing diagramcarrier sense and collision table 29. mii port timing limitscarrier sense and collision symbol definition minimum maximum unit tclh mii_crs, mii_clsn high time 80 ns a6455-01 mii_clsn mil_crs t clh 21145 preliminary datasheet 33 3.11 expansion rom and serial rom port dc specification table 30 lists the dc specifications for the expansion rom and serial rom ports. these specifications apply in any mode in which the ports are used. 3.12 expansion rom port timing this section describes the expansion rom port timing. 3.12.1 expansion rom read timing figure 15 shows the expansion rom read timing characteristics, and table 31 lists the expansion rom read timing limits. table 30. expansion rom and serial rom port dc specifications symbol definition condition minimum maximum unit v oh output high voltage i oh = C4 ma 2.4 v v ol output low voltage i ol = 4 ma 0.4 v v ih input high voltage 2.0 v v il input low voltage 0.8 v i oz 1 maximum tristate output leakage current v out = vdd or vss C10 10 m a note: 1. for sr_do and br_ce_l, the maximum value is 1.0 m a. figure 15. expansion rom read timing diagram a6457-01 t ads address=<7:2> oe=0, we=1 data<7:0> valid address<1> address<0> address<16> address<17> address=<15:8> t adh t ads t adh t elqx t elqv t ehqz t avav t oh t avqv br_ad<7:0> br_a<1> br_a<0> br_ce_l 21145 34 preliminary datasheet 3.12.2 expansion rom write timing figure 16 shows the expansion rom write timing characteristics, and table 32 lists the expansion rom write timing limits. table 31. expansion rom read timing specifications symbol parameter minimum maximum unit t avav read cycle time 240 ns t avqv address to output delay 220 ns t elqv br_ce_l to output delay 220 ns t elqx br_ce_l to output low impedance 0 ns t ehqz br_ce_l going high to output high impedance 2 pci_clk t oh output hold from br_ce_l change 0 ns t ads address setup to latch enable high 10 ns t adh address hold from latch enable high 10 ns figure 16. expansion rom write timing diagram table 32. expansion rom write timing specifications (sheet 1 of 2) symbol 1 parameter minimum unit t avav write cycle time 210 ns t eleh br_ce_l pulse width 210 ns t aveh address setup to br_ce_l going high 50 ns t dveh data setup to br_ce_l going high 50 ns a6458-01 t ads address=<7:2> oe=1, we=0 data<7:0> address<0> address<16> address<17> address=<15:8> t adh t ads t adh t aveh t dveh t eleh t ehax t ehdx t avav br_ad<7:0> br_a<1> br_a<0> br_ce_l address<1> 21145 preliminary datasheet 35 3.13 serial rom timing characteristics figure 17 shows the serial rom timing characteristics, and table 33 lists the characteristics. t ehdx data hold from br_ce_l going high 10 ns t ehax address hold from br_ce_l high 15 ns t ads address setup to latch enable high 10 ns t adh address hold from latch enable high 10 ns note: 1. there are no maximum specifications. table 32. expansion rom write timing specifications (sheet 2 of 2) symbol 1 parameter minimum unit figure 17. serial rom port timing diagram table 33. serial rom port timing characteristics symbol definition minimum maximum unit t ckh clock high time 350 ns t ckl clock low time 350 ns t css chip select setup time 150 ns t csh chip select hold time 0 ns t csl chip select low time 300 ns t dis data input setup time 150 ns t dih data input hold time 150 ns t pd data output delay time 550 ns t cz data output disable time 150 ns a6604 -01 sr_clk sr_di sr_do (read) sr_do (program) sr_cs t cz t cz t pd t pd t dih t sv t dis t css t cxl v ih v il v ih v il v ih v il v oh v ol v oh v ol t ckh t csh status valid 21145 36 preliminary datasheet 3.14 external register timing figure 18 shows the external register read timing characteristics, and figure 19 shows the write timing characteristics. table 34 lists the external register timing specifications for both read and write operations. figure 18. external register read timing diagram figure 19. external register write timing diagram table 34. external register timing specifications symbol parameter minimum maximum unit t eleh br_ce_l pulse width 240 ns read timing t pd br_ce_l low to br_ad<7:0> valid high 20 ns t ehqz br_ce_l high to br_ad<7:0> high impedance 20 ns write timing t s data setup time prior to br_ce_l 10 ns t h data hold after br_ce_l high 10 ns a6459-01 data valid t pd t ehqz br_ad<7:0> br_a<0> br_ce_l a6460-01 br_a<0> br_ce_l br_ad<7:0> t eleh t s t h data<7:0> 21145 preliminary datasheet 37 3.15 modem electrical parameters this section describes the modem write and read characteristics for the 21145. for more information about the modem characteristics for the 21145, see the 2 1145 phoneline/ethernet lan controller hardware reference manual . 3.16 write access to modem chipset figure 20 and table 35 describe a write access to the modem chipset. for more information about the sequence for a write access to the modem chipset, see the 2 1145 phoneline/ethernet lan controller hardware reference manual . figure 20. write access timing table 35. modem write access timing values symbol parameter minimum unit t css chip select set-up 15 ns t ads address set-up 45 ns t adh address hold 45 ns w/wh write pulse width 100 ns t dss data set-up 45 ns t dh data hold 15 ns t csh chip select hold 15 ns a6461-01 mdm_chip_sel mdm_wr mdm_a mdm w/wh t css t ads t dss t adh t dh t csh 21145 38 preliminary datasheet 3.16.1 read access to modem chipset figure 21 and table 36 describe a read access to the modem chipset. for more information about the sequence for a read access to the modem chipset, see the 2 1145 phoneline/ethernet lan controller hardware reference manual . figure 21. read access timing table 36. modem read access timing values symbol parameter minimum maximum unit t css chip select set-up 15 Cns t ads address set-up 45 C ns t adh address hold 45 C ns r/wh read pulse width 100 C ns t dd data delay C 90 ns t dh data hold 0 C ns t csh chip select hold 15 C ns a6462-01 mdm_chip_sel mdm_wr mdm_a mdm t css t css t ads t dd t adh t chs 21145 preliminary datasheet 39 4.0 mechanical specifications the 21145 is contained in a 176-pin tqfp package or a 144-pin tqfp package, as listed in table 37 . figure 22 shows the package markings. figure 23 shows the mechanical layout of the 176-pin package, and figure 24 that of the 144-pin package. all measurements are in mm. table 37. 21145 identifiers device identifier stepping marketing part number order code version status dc1116 b0 21145 de-nh978-aa 176tqfp production parts, 176 pin dc1116 b0 21145 de-nh978-ta 144tqfp production parts, 144 pin figure 22. 21145 package marking a6377-01 21145 de-nh978- xx dc1116 s*yyww*xxxxx i intel*(m)(c)*1998 pin 1 marketing part number device identifier order code site code/ date code/ wafer lot number (varies) copyright information 21145 40 preliminary datasheet figure 23. 176-pin tqfp package a5995-01 (4) 8.50 a detail a detail d detail e detail b detail c b d c e 24.00 0.05 26.00 0.20 (4) 8.50 24.00 0.05 26.00 0.20 1.60 0.13 x 0.15 max (top) 1.14 ref. 1.50 0.10 0.50 bsc. 0.70 0.6375 (4) r 0.15 typ. 3 ? 2 ? 3 ? 2 ? 1.00 0.10 0.525 0.10 0.10 0.03 1.40 0.05 r 0.20 typ. r 0.15 typ. 12 ? 1 ? 12 ? 1 ? 0.6375 0.26 typ. 0.125 0.30 0.05 0.05 0.03 2.34 0.22 +0.05/-0.025 (4) 3.00 0.13 x 0.15 max (btm) 21145 preliminary datasheet 41 figure 24. 144-pin tqfp package a6463-01 0.525 0.10 0.05 0.03 a // 0.13 c c - c - datum plane seating plane ccc - h - - basic dimension - reference dimension ( ) a c m ddd s b s 0 o - 7 o c detail "a" a2 (a) a1 l (ll) r notes: all dimensions are in millimeters. see detail "a" d d1 b e e e1 pin 1 pin # direction - b - - a - 21145 42 preliminary datasheet table 38. 144-pin lqfp package dimensions symbol dimension value (mm) ll lead length 1.00 reference 1 1. the value for this measurement is for reference only . e lead pitch 0.50 bsc 2 2. ansi y14.5mC1982 american national standard dimensioning and tolerancing, section 1.3.2, defines basic dimension (bsc) as: a numerical value used to describe the theoretically exact size, profile, orientation, or location of a feature or da tum target. it is the basis from which permissible variations are established by tolerances on other dimensions, in notes, or in fe a- ture control frames. l foot length 0.45 minimum to 0.75 maximum a package overall height 1.60 maximum a1 package standoff height 0.05 minimum a2 package thickness 1.35 minimum to 1.45 maximum b lead width 0.17 minimum to 0.27 maximum c lead thickness 0.09 minimum to 0.20 maximum ccc coplanarity 0.08 ddd lead skew 0.08 d package overall width 22.00 bsc d1 package width 20.00 bsc e package overall length 22.00 bsc e1 package length 20.00 bsc r ankle radius 0.08 minimum to 0.20 maximum support, products, and documentation if you need general information or support, call 1-800-628-8686 or visit intels website at: http://www.intel.com copies of documents that have an ordering number and are referenced in this document, a product catalog, or other intel literature may be obtained by calling 1-800-548-4725 or by visiting intels website for developers at: http://developer.intel.com |
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